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Advanced ASIC Chip Synthesis Using Synopsys® Design Compiler® Physical Compiler® and PrimeTime® 在線電子書 pdf 下載 txt下載 epub 下載 mobi 下載 2024

Advanced ASIC Chip Synthesis Using Synopsys® Design Compiler® Physical Compiler® and PrimeTime®
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Himanshu Bhatnagar 作者
Springer
譯者
2001-12-01 出版日期
353 頁數
USD 169.00 價格
Hardcover
叢書系列
9780792376446 圖書編碼

Advanced ASIC Chip Synthesis Using Synopsys® Design Compiler® Physical Compiler® and PrimeTime® 在線電子書 圖書標籤: IC後端  時序分析  教程  PT  DC  邏輯綜閤  這本書在哪兒可以買？  綜閤   

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Advanced ASIC Chip Synthesis Using Synopsys® Design Compiler® Physical Compiler® and PrimeTime® 在線電子書 epub 下載 mobi 下載 pdf 下載 txt 下載 2024

Advanced ASIC Chip Synthesis Using Synopsys® Design Compiler® Physical Compiler® and PrimeTime® 在線電子書 epub 下載 pdf 下載 mobi 下載 txt 下載 2024

Advanced ASIC Chip Synthesis Using Synopsys® Design Compiler® Physical Compiler® and PrimeTime® 在線電子書 pdf 下載 txt下載 epub 下載 mobi 下載 2024


Advanced ASIC Chip Synthesis Using Synopsys® Design Compiler® Physical Compiler® and PrimeTime® 在線電子書 用戶評價

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Advanced ASIC Chip Synthesis Using Synopsys® Design Compiler® Physical Compiler® and PrimeTime® 在線電子書 著者簡介

Advanced ASIC Chip Synthesis Using Synopsys® Design Compiler® Physical Compiler® and PrimeTime® 在線電子書 著者簡介

Advanced ASIC Chip Synthesis Using Synopsys® Design Compiler® Physical Compiler® and PrimeTime® 在線電子書 pdf 下載 txt下載 epub 下載 mobi 在線電子書下載

Advanced ASIC Chip Synthesis Using Synopsys® Design Compiler® Physical Compiler® and PrimeTime® 在線電子書 圖書描述

Advanced ASIC Chip Synthesis: Using Synopsys(R) Design Compiler(R) Physical Compiler(R) and PrimeTime(R), Second Edition describes the advanced concepts and techniques used towards ASIC chip synthesis, physical synthesis, formal verification and static timing analysis, using the Synopsys suite of tools. In addition, the entire ASIC design flow methodology targeted for VDSM (Very-Deep-Sub-Micron) technologies is covered in detail. The emphasis of this book is on real-time application of Synopsys tools, used to combat various problems seen at VDSM geometries. Readers will be exposed to an effective design methodology for handling complex, sub-micron ASIC designs. Significance is placed on HDL coding styles, synthesis and optimization, dynamic simulation, formal verification, DFT scan insertion, links to layout, physical synthesis, and static timing analysis. At each step, problems related to each phase of the design flow are identified, with solutions and work-around described in detail. In addition, crucial issues related to layout, which includes clock tree synthesis and back-end integration (links to layout) are also discussed at length. Furthermore, the book contains in-depth discussions on the basis of Synopsys technology libraries and HDL coding styles, targeted towards optimal synthesis solution. Target audiences for this book are practicing ASIC design engineers and masters level students undertaking advanced VLSI courses on ASIC chip design and DFT techniques.

Advanced ASIC Chip Synthesis Using Synopsys® Design Compiler® Physical Compiler® and PrimeTime® 在線電子書 下載 mobi epub pdf txt 在線電子書下載
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