Introduction to Logical Synthesis Using Verilog HDL 在线电子书 pdf 下载 txt下载 epub 下载 mobi 下载 2024

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Reese, Robert B./ Thornton, Mitchell A. 作者

Morgan & Claypool

译者

1905-6 出版日期

84 页数

$ 39.55 价格

Pap

丛书系列

9781598291063 图书编码

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Introduction to Logical Synthesis Using Verilog HDL 在线电子书 epub 下载 mobi 下载 pdf 下载 txt 下载 2024

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Introduction to Logic Synthesis Using Verilog HDL explains how to write accurate Verilog descriptions of digital systems that can be synthesized into digital system netlists with desirable characteristics. The book contains numerous Verilog examples that begin with simple combinational networks and progress to synchronous sequential logic systems. Common pitfalls in the development of synthesizable Verilog HDL are also discussed along with methods for avoiding them. The target audience is anyone with a basic understanding of digital logic principles who wishes to learn how to model digital systems in the Verilog HDL in a manner that also allows for automatic synthesis. A wide range of readers, from hobbyists and undergraduate students to seasoned professionals, will find this a compelling and approachable work. The book provides concise coverage of the material and includes many examples, enabling readers to quickly generate high-quality synthesizable Verilog models.

Introduction to Logical Synthesis Using Verilog HDL 在线电子书下载 mobi epub pdf txt 在线电子书下载

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