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《高速CMOS电路设计Logical Effirt方法(英文版)》讲述如何获得高速CMOS电路，这正是高速集成电路设计师们渴望获得的技术。在设计中，我们往往面对无数的选择，《高速CMOS电路设计Logical Effirt方法(英文版)》将告诉我们如何将这些选择变得更容易和更有技巧。《高速CMOS电路设计Logical Effirt方法(英文版)》提供了一个简单而普遍有效的方法，用于估计拓扑、电容等因素造成的延迟。

《高速CMOS电路设计Logical Effirt方法(英文版)》实用性强，适合集成电路设计师以及相关专业的师生。

Ivan Sutherland，著名计算机科学家。因对计算机图形学和电子设计领域的开创性贡献先后获得1988年图灵奖和1998年冯·诺依曼奖。美国科学院院士、美国工程院院士和ACM会士。现任Sun公司副总裁。

Bob Sproull，著名计算机科学家，美国工程院院士。现为Sun公司副总裁兼研究中心主任。Sutherland的长期合作者。

David Harris，Harvey Mudd学院副教授。曾参与Intel安腾和奔腾Ⅱ的电路设计。除本书外，他还与Weste合著了名作CMOS VLSIDesign：A Circuits and Systems Perspective。

1 The Method of Logical Effort 1.1 Introduction 1.2 Delay in a Logic Gate 1.3 Multistage Logic Networks 1.4 Choosing the Best Number of Stages 1.5 Summary of the Method 1.6 A Look Ahead 1.7 Exercises 2 Design Examples 2.1 The AND Function of Eight Inputs 2.2 Decoder 2.3 Synchronous Arbitration 2.4 Summary 2.5 Exercises 3 Deriving the Method of Logical Effort 3.1 Model of a Logic Gate 3.2 Delay in a Logic Gate 3.3 Minimizing Delay along a Path 3.4 Choosing the Length of a Path 3.5 Using the Wrong Number of Stages 3.6 Using the Wrong Gate Size 3.7 Summary 3.8 Exercises 4 Calculating the Logical Effort of Gates 4.1 Definitions of Logical Effort 4.2 Grouping Input Signals 4.3 Calculating Logical Effort 4,4 Asymmetric Logic Gates 4.5 Catalog of Logic Gates 4.6 Estimating Parasitic Delay 4.7 Properties of Logical Effort 4.8 Exercises 5 Calibrating the Model 5.1 Calibration Technique 5.2 Designing Test Circuits 5.3 Other Characterization Methods 5.4 Calibrating Special Circuit Families 5.5 Summary 5.6 Exercises 6 Asymmetric Logic Gates 6.1 Designing Asymmetric Logic Gates 6.2 Applications of Asymmetric Logic Gates 6.3 Summary 6.4 Exercises 7 Unequal Rising and Falling Delays 7.1 Analyzing Delays 7.2 Case Analysis 7.3 Optimizing CMOS P/N Ratios 7.4 Summary 7.5 Exercises 8 Circuit Families 8.1 Pseudo-NMOS Circuits 8.2 Domino Circuits 8.3 Transmission Gates 8.4 Summary 8.5 Exercises 9 Forks of Amplifiers 9.1 The Fork Circuit Form 9.2 How Many Stages Should a Fork Use? 9.3 Summary 9.4 Exercises 10 Branches and Interconnect 10.1 Circuits That Branch at a Single Input 10.2 Branches after Logic 10.3 Circuits That Branch and Recombine 10.4 Interconnect 10.5 A Design Approach 10.6 Exercises 11 Wide Structures 11.1 An n-input AND Structure 11.2 An n-input Muller C-element 11.3 Decoders 11.4 Multiplexers 11.5 Summary 11.6 Exercises 12 Conclusions 12.1 The Theory of Logical Effort 12.2 Insights from Logical Effort 12.3 A Design Procedure 12.4 Other Approaches to Path Design 12.5 Shortcomings of Logical Effort 12.6 Parting Words Cast of CharactersReference Process ParametersSolutions to Selected ExercisesBIBLIOGRAPHYINDEX
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