VHDL Modeling for Digital Design Synthesis 在线电子书 pdf 下载 txt下载 epub 下载 mobi 下载 2024

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Yu-Chin Hsu 作者

Springer

译者

1995-07-31 出版日期

375 页数

USD 249.00 价格

Hardcover

丛书系列

9780792395973 图书编码

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VHDL Modeling for Digital Design Synthesis 在线电子书 epub 下载 mobi 下载 pdf 下载 txt 下载 2024

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VHDL Modeling for Digital Design Synthesis 在线电子书 pdf 下载 txt下载 epub 下载 mobi 在线电子书下载

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VHDL is a hardware description language that allows the specification of a digital system over different levels of abstraction. It supports behavior specification during the early stages of a design process and structural specification during the later implementation stages. Originally introduced as a hardware description language that permitted the simulation of digital designs, VHDL is now increasingly used for design specifications that are given as the input to synthesis tools which translate the specifications into netlists from which the physical systems can be built. One problem with this is that not all of its constructs are useful in synthesis. VHDL has data structures, such as files and pointers, which are useful for simulation but not for actual synthesis. As a result, synthesis tools accept only subsets of VHDL. VHDL Modeling for Digital Design Synthesis covers the synthesis aspects of VHDL, keeping the simulation specifics to a minimum. Audience: Working professionals as well as graduate or undergraduate students who can use the book to get acquainted with VHDL and to learn how it can be used in modeling or digital design.

VHDL Modeling for Digital Design Synthesis 在线电子书下载 mobi epub pdf txt 在线电子书下载

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