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System-on-Chip Test Architectures

简体网页||繁体网页
Laung-Terng Wang 作者
Morgan Kaufmann
译者
2007-12-4 出版日期
896 页数
USD 84.95 价格
Hardcover
丛书系列
9780123739735 图书编码

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System-on-Chip Test Architectures 在线电子书 epub 下载 mobi 下载 pdf 下载 txt 下载 2024

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System-on-Chip Test Architectures 在线电子书 pdf 下载 txt下载 epub 下载 mobi 下载 2024



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System-on-Chip Test Architectures 在线电子书 图书描述

Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40 per cent of today's overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.It emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples. It has the most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book. It covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits. It discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing. It includes practical problems at the end of each chapter for students.

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