Chapter1ReviewofLogicDesignFundamentals1.1CombinationalLogic1.2BooleanAlgebraandAlgebraicSimplification1.3KarnaughMaps1.4DesigningwithNANDandNORGates1.5HazardsinCombinationalCircuits1.6Flip-FlopsandLatches1.7MealySequentialCircuitDesign1.8MooreSequentialCircuitDesign1.9EquivalentStatesandReductionofStateTables1.10SequentialCircuitTiming1.11TristateLogicandBusses1.12ProblemsChapter2IntroductiontoVHDL2.1Computer-AidedDesign2.2HardwareDescriptionLanguages2.3VHDLDescriptionofCombinationalCircuits2.4VHDLModules2.5SequentialStatementsandVHDLProcesses2.6ModelingFlip-FlopsUsingVHDLProcesses2.7ProcessesUsingWaitStatements2.8TwoTypesofVHDLDelays:TransportandInertialDelays2.9Compilation,Simulation,andSynthesisofVHDLCode2.10VHDLDataTypesandOperators2.11SimpleSynthesisExamples2.12VHDLModelsforMultiplexers2.13VHDLLibraries2.14ModelingRegistersandCountersUsingVHDLProcesses2.15BehavioralandStructuralVHDL2.16Variables,Signals,andConstants2.17Arrays2.18LoopsinVHDL2.19AssertandReportStatements2.20ProblemsChapter3AdditionalTopicsinVHDL3.1VHDLFunctions3.2VHDLProcedures3.3Attributes3.4CreatingOverloadedOperators3.5Multi-ValuedLogicandSignalResolution3.6TheIEEE9-ValuedLogicSystem3.7SRAMModelUsingIEEE11643.8ModelforSRAMRead/WriteSystem3.9Generics3.10NamedAssociation3.11GenerateStatements3.12FilesandTEXTIO3.13ProblemsChapter4DesignExamples4.1BCDtoSeven-SegmentDisplayDecoder4.2ABCDAdder4.332-BitAdders4.4TrafficLightController4.5StateGraphsforControlCircuits4.6ScoreboardandController4.7SynchronizationandDebouncing4.8AAdd-and-ShiftMultiplier4.9ArrayMultiplier4.10ASignedInteger/FractionMuliplier4.11KeypadScanner4.12BinaryDividers4.13ProblemsChapter5SMChartsandMicroprogramming5.1StateMachineCharts5.2DerivationofSMCharts5.3RealizationofSMCharts5.4ImplementationoftheDiceGame5.5ProblemsChapter6Floating-PointArithmetic6.1RepresentationofFloating-PointNumbers6.2Floating-PointMultiplication6.3Floating-PointAddition6.4OtherFloating-PointOperations6.5ProblemsChapter7HardwareTestingandDesignforTestability7.1TestingCombinationalLogic7.2TestingSequentialLogic7.3ScanTesting7.4BoundaryScan7.5Built-InSelf-Test7.6ProblemsChapter8AdditionalDesignExamples8.1DesignofaWristwatch8.2MemoryTimingModels8.3AUniversalAsynchronousReceiverTransmitter8.4ProblemsAppendixAVH
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