1 Introduction ............................................................... 1
1.1 Overview ............................................................... 1
1.2 Chapter Outline ........................................................ 3
1.2.1 Section I: Pipelined ADC Design .............................. 3
1.2.2 Section II: Pipelined ADC Enhancement Techniques ......... 4
Part I Pipelined ADC Design
2 ADC Architectures ....................................................... 7
2.1 Overview ............................................................... 7
2.2 Factors Which Determine ADC Resolution and Linearity ............ 7
2.3 ADC Architectures ................................................... 11
2.4 ADC Figure-of-Merit ................................................. 12
2.5 Flash ADC ............................................................ 12
2.6 SARADC ............................................................. 14
2.7 Sub-sampling ......................................................... 16
2.8 Summary .............................................................. 17
3 Pipelined ADC Architecture Overview ................................ 19
3.1 Overview .............................................................. 19
3.2 Pipelined ADC Introduction .......................................... 19
3.3 Multiplying Digital to Analog Converter (MDAC) .................. 21
3.4 Opamp DC Gain Requirements ...................................... 23
3.5 Opamp Bandwidth Requirements .................................... 26
3.6 Thermal Noise Requirements ......................................... 28
3.7 MDAC Design: Capacitor Matching/Linearity ...................... 29
3.8 Error Correction in Pipelined ADCs: Relaxed Sub-ADC
Requirements ......................................................... 31
3.9 Sub-ADC Design: Comparator ....................................... 35
3.10 Front-End Sample-and-Hold ........................................ 36
3.11 Summary ............................................................. 38
4 Scaling Power with Sampling Rate in an ADC ........................ 39
4.1 Overview .............................................................. 39
4.2 ADC Power as a Function of Sampling Rate ........................ 39
4.3 Digital Versus Analog Power ......................................... 40
4.4 Weak Inversion Model: EKV ........................................ 42
4.5 Weak Inversion Issues: Mismatch .................................... 43
4.6 Current Scaling: Multiple Design Corners . . . ........................ 45
4.7 Current Scaling: Bias Point Sensitivity .............................. 45
4.8 Current Scaling: IR Drops ............................................ 46
4.9 Summary .............................................................. 48
5 State of the Art Pipelined ADC Design ................................ 49
5.1 Overview .............................................................. 49
5.2 Calibration in Pipelined ADCs ....................................... 49
5.2.1 Review of Error Sources ....................................... 50
5.2.2 Gain Error Correction ......................................... 50
5.2.3 DAC Error Correction ......................................... 52
5.2.4 Foreground Calibration ........................................ 52
5.2.5 Background Calibration ....................................... 53
5.2.6 Rapid Calibration of ADC Errors ............................. 54
5.3 Power Scalability with Respect to Sampling Rate ................... 56
5.4 Power Reduction Techniques in Pipelined ADCs .................... 56
5.4.1 Front-End S/H Removal ....................................... 56
5.4.2 Open-Loop Amplifier Approach ............................... 58
5.4.3 Comparator Based Switched Capacitor Circuits .............. 60
5.5 Summary .............................................................. 61
Part II Pipelined ADC Enhancement Techniques
6 Rapid Calibration of DAC and Gain Errors in a Multi-bit
Pipeline Stage ............................................................ 65
6.1 Overview .............................................................. 65
6.2 Motivation ............................................................ 65
6.2.1 Why Are DAC Errors Important to Correct? ................. 66
6.3 Rapid DAC + Gain Calibration Architecture ........................ 66
6.3.1 Measurement of Missing Codes Due to DAC
and Gain Errors ................................................ 67
6.3.2 Correction of Missing Codes .................................. 68
6.3.3 Mismatch Between ADCs ..................................... 69
6.3.4 Simulation Results ............................................. 70
6.4 Circuit Implementation ............................................... 73
6.4.1 Front-End Sample-and-Hold ................................... 74
6.4.2 5-Bit Flash ADC ............................................... 75
6.4.3 4-Bit MDAC ................................................... 75
6.4.4 Backend Pipelined ADC ....................................... 77
6.4.5 Digital Calibration ............................................. 78
6.5 Testing ................................................................ 78
6.5.1 PCB ............................................................ 79
6.5.2 Test Setup ...................................................... 79
6.6 Measured Results ..................................................... 81
6.6.1 INL/DNL Plots ................................................ 81
6.6.2 SNDR/SFDR Plots ............................................. 81
6.6.3 Calibration Time ............................................... 82
6.7 Summary .............................................................. 84
7 A Power Scalable and Low Power Pipelined ADC .................... 85
7.1 Overview .............................................................. 85
7.2 Power Scalable Architecture ......................................... 85
7.3 Current Modulated Power Scaling (CMPS) . . ........................ 88
7.4 Current Switching Issues ............................................. 91
7.5 Hybrid Power Scaling ................................................ 92
7.6 Detailed Trigger Analysis ............................................ 93
7.7 Design of the Digital State Machine ................................. 97
7.8 Rapid Power-On Opamps ........................................... 100
7.8.1 Conventional Approach: Switched Bias Opamp ............. 100
7.8.2 Rapid Power-On Opamps Used in This Work ............... 101
7.8.3 Benefits of Feedback Based Biasing: Increased Output
Resistance ..................................................... 104
7.8.4 Opamp Specification/Characterization ....................... 105
7.9 Common Mode Feed Back (CMFB) for Rapid
Power-On Opamp ................................................... 109
7.10 Power Reduction Through Current Modulation .................. 111
7.10.1 Common Mode Feed Back (CMFB) for
Different Opamp Modes .................................. 112
7.11 Sample-and-Hold (S/H) ........................................... 113
7.12 1.5-bit MDAC ..................................................... 114
7.13 Sub-ADC Comparators ............................................ 114
7.14 Bias Circuits ....................................................... 115
7.15 Non-overlapping Clock Generator ................................ 116
7.16 Reference voltages ................................................ 117
7.17 Digital Error Correction ........................................... 118
7.18 Experimental Implementation: PCB .............................. 118
7.19 Experimental Implementation: Test Setup . . ...................... 118
7.20 Measured Results .................................................. 120
7.21 Current Scaled Power ............................................. 121
7.21.1 Power Reduction Mode: Static Accuracy ................. 127
7.21.2 Power Scalable ADC: Current Scaling ................... 131
7.22 Power Scalable ADC: Power Scaling Using CMPS .............. 137
7.23 Summary ........................................................... 144
8 A Sub-sampling ADC with Embedded Sample-and-Hold ........... 147
8.1 Overview ............................................................ 147
8.2 Motivation .......................................................... 147
8.3 Embedded S/H Technique .......................................... 148
8.4 Circuit Implementation ............................................. 151
8.4.1 ADC Architecture ............................................ 151
8.4.2 Rapid Power-On Opamp ...................................... 152
8.4.3 Generation of Delayed Clock F2D ........................... 153
8.5 Test Setup: PCB .................................................... 155
8.6 Test Setup: Equipment .............................................. 156
8.7 Measured Results ................................................... 156
8.7.1 SNDR Versus Input Frequency ............................... 157
8.7.2 Power Versus Sampling Rate ................................. 158
8.7.3 Tdelay Versus Settling Time: Robustness of Technique ...... 159
8.8 Summary ............................................................ 160
9 A Capacitive Charge Pump Based Low Power
Pipelined ADC .......................................................... 163
9.1 Overview ............................................................ 163
9.2 Motivation .......................................................... 164
9.3 Architecture: Capacitive Charge Pump Based Gain ............... 164
9.4 Effect of Parasitic Capacitors ....................................... 168
9.5 Unity Gain Buffer Topology ....................................... 170
9.5.1 Linearity of Source Follower in a Sampled System ......... 175
9.5.2 Signal Swing of Source Follower ............................ 176
9.6 Noise Analysis of Capacitive Charge Pump Based MDAC ....... 177
9.7 Calibration of Pipeline Stages ...................................... 181
9.7.1 Foreground Calibration in Detail ............................. 181
9.8 Theoretical Power Savings ......................................... 183
9.9 Design Specifications ............................................... 185
9.10 Circuit Design ..................................................... 186
9.10.1 ADC Top Level Topology ................................ 186
9.10.2 Front-End Sample-and-Hold .............................. 187
9.10.3 MDAC and Unity Gain Amplifier . . ...................... 187
9.10.4 Sub-ADC .................................................. 189
9.10.5 Digital State Machine ..................................... 190
9.10.6 Analog Test-Mux .......................................... 190
9.11 Testing ............................................................. 191
9.11.1 PCB ........................................................ 191
9.11.2 Test Setup ................................................. 191
9.12 Measured Results .................................................. 193
9.12.1 Measured ADC SNDR Variation . . . ...................... 194
9.12.2 ADC FFTs ................................................. 196
9.12.3 INL/DNL plots ............................................ 199
9.13 Summary ........................................................... 199
10 Summary ................................................................ 201
10.1 Summary ........................................................... 201
References .................................................................... 203
Index .......................................................................... 209
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