SystemVerilog For Design 在线电子书 pdf 下载 txt下载 epub 下载 mobi 下载 2024

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Stuart Sutherland 作者

Springer

译者

2003-06-30 出版日期

402 页数

USD 130.00 价格

Hardcover

丛书系列

9781402075308 图书编码

SystemVerilog For Design 在线电子书图书标签: systemverilog verilog ic

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发表于2024-09-10

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SystemVerilog For Design 在线电子书 epub 下载 mobi 下载 pdf 下载 txt 下载 2024

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SystemVerilog is a rich set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language (Verilog HDL). These extensions address two major aspects of HDL based design. First, modeling very large designs with concise, accurate, and intuitive code. Second, writing high-level test programs to efficiently and effectively verify these large designs. This book, SystemVerilog for Design, addresses the first aspect of the SystemVerilog extensions to Verilog. Important modeling features are presented, such as two-state data types, enumerated types, user-defined types, structures, unions, and interfaces. Emphasis is placed on the proper usage of these enhancements for simulation and synthesis. A companion to this book, SystemVerilog for Verification, covers the second aspect of SystemVerilog.

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