SystemVerilog for Verification teaches the reader how to use the power of the new SystemVerilog testbench constructs plus methodology without requiring in-depth knowledge of Object Oriented Programming or Constrained Random Testing. The book covers the SystemVerilog verification constructs such as classes, program blocks, C interface, randomization, and functional coverage. SystemVerilog for Verification also reviews some design topics such as interfaces and array types. There are extensive code examples and detailed explanations. The book will be based on Synopsys courses, seminars, and tutorials that the author developed for SystemVerilog, Vera, RVM, and OOP. Concepts will be built up chapter-by-chapter, and detailed testbench using these topics will be presented in the final chapter. SystemVerilog for Verification concentrates on the best practices for verifying your design using the power of the language.
具体描述
读后感
anyone who can thoroughly understand this book can become the expert of sv verification.
评分正在读，先记录一下感受。 翻译的基本上还可以。就我读过的专业书籍来说，算是平均之上吧。 能看得出来翻译的人是业内人士，而且对书中的例子大概也进行了调试，否则不会出现改动原书的代码的状况。 在第八章我已经发现了至少两个地方对原书代码的改动。很不幸的是，都改错了...
评分the best book of introducing verifcation using SV. It is worth taking a careful look. And you should run all the codes by yourself with VCS/NC/modelsim
评分anyone who can thoroughly understand this book can become the expert of sv verification.
评分the best book of introducing verifcation using SV. It is worth taking a careful look. And you should run all the codes by yourself with VCS/NC/modelsim
用户评价
读这本书太费劲了，英文读不懂，中文更读不懂。把asic-world.com上systemverilog的例子全做一遍，结合着读这部书会好一点，一点个人体会。
评分@Quietstream要offer
评分@Quietstream要offer
评分不会吧，连这书都有？ 好想把它读懂……
评分不会吧，连这书都有？ 好想把它读懂……
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