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Verilog 在线电子书 pdf 下载 txt下载 epub 下载 mobi 下载 2024

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Shivakumar Chonnad 作者

Springer

译者

2004-09-23 出版日期

272 页数

USD 159.00 价格

Hardcover

丛书系列

9780387228341 图书编码

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发表于2024-11-27

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Verilog 在线电子书 epub 下载 mobi 下载 pdf 下载 txt 下载 2024

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This book addresses "front end" questions and issues encountered in using the Verilog HDL, during all the stages of Hardware Design, Synthesis and Verification. The issues discussed in the book are typically encountered in both ASIC design projects as well as in Soft IP designs. These issues are addressed in a simple Q&A format. Since each issue is independently dealt with and explained in detail, this book acts as an important source of reference for the Verilog users. Each of the FAQs will be illustrated with figures and tables as required. The latest Verilog-2001 and SystemVerilog have also been referred to in this book. With the increasing complexity of ASICs being designed these days, the decisions that one makes in any of the stages of Design, Synthesis or Verification has profound effects on these three stages. This book presents the intricacies of these inter-dependent issues in the context of the Verilog HDL.

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