Dake Liu is Professor of the chair and the Director of Computer Engineering Division, Department of Electrical Engineering at Linköping University. He received his Ph.D. (Tekn. Dr.) degree from Linköping University in Feb. 1995.

Dake Liu performs his research of Computer architecture focusing on architectures of application specific instruction set processors (ASIP) and on-chip multi-core integrations based on VLSI. His research goal is to explore different processor architectures and inter processor architectures.

Dake Liu is the co-founder of FreeHand DSP AB, (VIA tech Sweden AB, Liljeholmsstranden 5, S-117 43, Stockholm). Freehad DSP was acquired by VIA technologies in 2001. Dake Liu is the co-founder of Coresonic AB. Dake Liu was a senior ASIC designer and low power design specialist in Ericsson Microelectronics, Stockholm, Sweden (Infineon Technologies Wireless Solutions Sweden AB) since 1995 to 1998.

刘大可早年毕业于北方交通大学。后赴瑞典留学，于1992和1994年分别获得瑞典林雪平大学副博士、工学博士学位。刘大可曾任爱立信瑞典(Ericsson)微电子集团高级研究员及高级设计师，现兼任威盛瑞典董事和威盛瑞典资深首席科学官。作为集成电路和处理器研究与设计方面的著名专家,刘大可在移动通讯手机数字信号处理系统、移动通讯基带数字信号处理器、互联网关语音系统、可编程专用网络处理器、超高速图片(JPEG)压缩数字信号处理器、数字信号处理器通用集成设计环境等方面取得了世界领先的科研成果。

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This book provides design methods for Digital Signal Processors and Application Specific Instruction set Processors, based on the author's extensive, industrial design experience. Top-down and bottom-up design methodologies are presented, providing valuable guidance for both students and practicing design engineers.

Coverage includes design of internal-external data types, application specific instruction sets, micro architectures, including designs for datapath and control path, as well as memory sub systems. Integration and verification of a DSP-ASIP processor are discussed and reinforced with extensive examples.

* Instruction set design for application specific processors based on fast application profiling

* Micro architecture design methodology

* Micro architecture design details based on real examples

* Extendable architecture design protocols

* Design for efficient memory sub systems (minimizing on chip memory and cost)

* Real example designs based on extensive, industrial experiences