《SystemVerilog验证(测试平台编写指南原书第2版)》可以作为学习SystemVerilog验证语言的初级阶段读物。书中描述了语言的工作原理并且包含了很多例子，这些例子演示了如何使用面向对象编程(OOP)的方法建立一个基本的、由覆盖率驱动并且受约束的随机分层测试平台。
具体描述
读后感
the best book of introducing verifcation using SV. It is worth taking a careful look. And you should run all the codes by yourself with VCS/NC/modelsim
评分To read this book, you should have basic knowledge of Verilog. There are many examples in this book, very easy to understand. It's an introduction book for SystemVerilog Verification. If you want learn the language in depth, go IEEE1800 or VMM. You should...
评分the best book of introducing verifcation using SV. It is worth taking a careful look. And you should run all the codes by yourself with VCS/NC/modelsim
评分anyone who can thoroughly understand this book can become the expert of sv verification.
评分anyone who can thoroughly understand this book can become the expert of sv verification.
用户评价
验证入门必修，狂啃中。。。
评分经典的绿皮书
评分一本非常好的概览之作
评分验证必备，写的很好！对SV语法理解、CDV验证思想建立、验证平台的架构理解都很有好处。但是翻译的有点水，好多印刷错误和翻译错误。可以配合原版书本看！
评分验证入门必修，狂啃中。。。
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